The present invention relates generally to integrated circuit devices and, more particularly, to measurement of partially depleted silicon-on-insulator CMOS circuit leakage power under different steady state switching conditions.
For complementary metal oxide semiconductor (CMOS) products manufactured in partially depleted silicon-on-insulator (PDSOI) technology, the leakage power in the idle state may be different than the leakage power in the operating state because of metal oxide semiconductor field effect transistor (MOSFET) threshold voltage dependency on switching history. The switching frequency of circuits and the duty cycle vary considerably across the product, and thus the leakage power of the product cannot be simply derived from the quiescent leakage current (Iddq) measurements as is the case for bulk silicon technology.
In a CMOS circuit in PDSOI technology, the delay is dependent on its switching history. When a circuit first switches after sitting idle for a few ms or more (the first switch being referred to as “1SW” herein) it will have a longer or shorter delay than when it switches again within a few nanoseconds (the second switch being referred to as “2SW” herein). If the same circuit is switching on a regular basis, every few nanoseconds (ns) or less, it will have a third delay characteristic of steady-state (SS) operation. This steady state delay will itself depend on the details of the repetitive switching pattern.
The variations in delay are as a result of shifts in the MOSFET threshold voltage arising from floating body-effects. The shifts in MOSFET threshold voltages based on circuit switching history also result in shifts in the leakage currents. Accordingly, a CMOS product in an idle state will have a different leakage power (leakage current×power supply voltage) than when it is in a “working state” when the circuits are switching. The differences in leakage power may be substantial. For example, a 20 millivolt (mV) shift in threshold voltage and associated 2.5% change in delay correspond to 50% increase in leakage current, which translates to a 50% increase in leakage power. Thus, in order to project the leakage power of a product in its operating state, the leakage current in the idle state (IS) and in the steady state (SS), with different frequencies and pulse widths, should be monitored in the manufacturing line on a regular basis.
The measurement of SOI switching history to get leakage current estimates requires input pulse widths of a few nanoseconds or less along with picosecond (ps) time resolution. It also requires knowledge of the dependence of history and current on threshold voltage for the hardware under consideration. Typically, such history measurements have been made as bench tests on limited hardware using high speed probing techniques and equipment. These measurements are difficult to perform during processing in a manufacturing environment, due to such problems as noise, shielding, and test time. Bench measurements have shown that the PD-SOI history is often 10-15% in present PDSOI CMOS technologies, and it is a strong function of device design. In addition, history variation across a wafer may be in excess of 5%. Recently, a scheme has been described for measuring SOI 1SW-2SW history using a self-calibrating, self-timed technique with direct current (DC) signal inputs and outputs. Such a circuit, however, does not allow direct measurement or inference of leakage current under different steady state switching conditions.